HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 445

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

10.2.8
TRSCER specifies whether or not transmit and receive status information reported by bits in the
EtherC/E-DMAC status register is to be indicated in the corresponding descriptor. The bits in this
register correspond to EtherC/E-DMAC status register EESR[15 to 0]. When a bit is cleared to 0,
the transmit status (EESR[15 to 8]) is indicated in the TFE bit of the transmit descriptor, and the
receive status (EESR[7 to 0]) is indicated in the RFE bit of the receive descriptor. When a bit is set
to 1, the occurrence of the corresponding source is not indicated in the descriptor. After the chip is
reset, all bits are cleared to 0.
For the corresponding bit sources, see section 10.2.6, EtherC/E-DMAC Status Register (EESR).
430
Initial value:
Initial value:
Initial value:
Tx/Rx Status Copy Enable Register (TRSCER)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
RMAFCE
R/W
31
—
—
15
—
—
0
0
7
0
30
—
—
14
—
—
—
—
0
0
6
0
29
—
—
13
—
—
—
—
0
0
5
0
RRFCE RTLFCE RTSFCE PRECE CERFCE
ITFCE
R/W
R/W
. . .
. . .
. . .
. . .
12
0
4
0
CNDCE DLCCE
R/W
R/W
19
—
—
11
0
0
3
0
R/W
R/W
18
—
—
10
0
0
2
0
CDCE
R/W
R/W
17
—
—
0
9
0
1
0
TROCE
R/W
R/W
16
—
—
0
8
0
0
0