HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 772

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 4—Module Stop 4 (MSTP4): Specifies halting the clock supply to the DMAC. When MSTP4
bit is set to 1, the supply of the clock to the DMAC is halted. When the clock halts, the DMAC
retains its pre-halt state. When MSTP4 is cleared to 0 and the DMAC begins running again, its
starts operating from its pre-halt state. Set this bit while the DMAC is halted; this bit cannot be set
while the DMAC is operating (transferring data).
Bit 4: MSTP4
0
1
Bit 3—Module Stop 3 (MSTP3): Specifies halting the clock supply to the DSP unit. When the
MSTP3 bit is set to 1, the supply of the clock to the DSP unit is halted. When the clock halts, the
operation result prior to the halt is retained. This bit should be set when the DSP unit is halted.
When the DSP unit is halted, no instructions with a DSP register, MACH, or MACL as an operand
can be used.
Bit 3: MSTP3
0
1
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the 16-bit free-running
timer (FRT). When the MSTP1 bit is set to 1, the supply of the clock to the FRT is halted. When
the clock halts, all FRT registers are initialized except the FRT interrupt vector register in INTC,
which holds its previous value. When MSTP1 is cleared to 0 and the FRT begins running again, its
starts operating from its initial state.
Bit 1: MSTP1
0
1
Bit 0—Reserved: This bit always read 0. The write value should always be 0.
762
Description
FRT running
Clock supply to FRT halted
Description
DMAC running
Clock supply to DMAC halted
Description
DSP running
Clock supply to DSP halted
(Initial value)
(Initial value)
(Initial value)