HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 477

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 8—Acknowledge/Transfer Mode Bit (AM): In dual address mode, this bit selects whether the
DACK signal is output during the data read cycle or write cycle. In single-address mode, it selects
whether to transfer data from memory to device or from device to memory. The AM bit is
initialized to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 8: AM
0
1
Bit 7—Acknowledge Level Bit (AL): Selects whether the DACK signal is an active-high signal or
an active-low signal. The AL bit is initialized to 0 by a reset and in standby mode. Its value is
retained during a module standby.
Bit 7: AL
0
1
Bit 6—DREQ Select Bit (DS): Selects the DREQ input detection used. When 0 (level detection) is
set to bit DS, set 0 (cycle-steal mode) to the transfer bus mode bit (TB). When 0 is set to bit DS
and 1 (burst mode) is set to bit TB, system operations are not guaranteed. The DS bit is initialized
to 0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 6: DS
0
1
Bit 5—DREQ Level Bit (DL): Selects the DREQ input detection level. The DL bit is initialized to
0 by a reset and in standby mode. Its value is retained during a module standby.
Bit 5: DL
0
1
462
Description
DACK output in read cycle (dual address mode)/transfer from memory
to device (single address mode)
DACK output in write cycle (dual address mode)/transfer from device to
memory (single address mode)
Description
DACK is an active-low signal
DACK is an active-high signal
Description
Detected by level
Can be set only in cycle-steal mode
Detected by edge
Description
When DS is 0, DREQ is detected by low level; when DS is 1, DREQ is
detected at falling edge
When DS is 0, DREQ is detected by high level; when DS is 1, DREQ is
detected at rising edge
(Initial value)
(Initial value)
(Initial value)
(Initial value)