HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 538

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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12.4.4
Either the rising edge or falling edge can be selected for input capture input using the IEDG bit in
TCR. Figure 12.8 shows the timing when the rising edge is selected (IEDG = 1).
When the input capture signal is input when FICR is read (upper-byte read), the input capture
signal is delayed by one cycle of P . Figure 12.9 shows the timing.
Input capture
Input capture
Input capture
Input capture
Figure 12.9 Input Capture Signal Timing (Input Capture Input when FICR is Read)
input pin
input pin
signal
signal
Input Capture Input Timing
P
P
Figure 12.8 Input Capture Signal Timing (Normal)
FICR upper-byte read cycle
523

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