HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 318

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

When a single write is performed in burst write mode, the synchronous DRAM setting is for a
burst length of 4. After data is written in Tc1, empty writes are performed in Tc2, Tc3, and Tc4 by
driving the DQMxx signal high.
These empty cycles increase the memory access time and tend to reduce program execution speed
and DMA transfer speed. Therefore, unnecessary cache-through area accesses should be avoided,
and copy-back should be selected for the cache setting. Also, in DMA transfer, it is important to
use a data structure that allows transfer in 16-bit units.
CKIO
A24–A11
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31–D0
DACKn*
Note: * DACKn waveform when active-low is specified.
Figure 7.23 (a) Basic Burst Write Timing (Auto-Precharge) I : E other than 1 : 1
Tr
Tc1
Tc2
Tc3
Tc4
Trwl
Tap
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