HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 419

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

9.3.4
MII registers in the PHY-LSI are accessed via the SH7615’s MII control register. Connection is
made as a serial interface in accordance with the MII frame format specified in IEEE802.3u.
MII Management Frame Format: The format of an MII management frame is shown in figure
9.5. To access an MII register, a management frame is implemented by the program in accordance
with the procedures shown in MII Register Access Procedure.
MII Register Access Procedure: The program accesses MII registers via the MII control register.
Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release,
and independent bus release. Examples 1 through 4 below show the register access timing. The
timing will differ depending on the PHY-LSI type.
1. The MII register write procedure is shown in figure 9.6 (a).
2. The bus release procedure is shown in figure 9.6 (b).
3. The MII register read procedure is shown in figure 9.6 (c).
4. The independent bus release procedure is shown in figure 9.6 (d).
PRE:
ST:
OP:
PHYAD: Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB).
TA:
DATA:
IDLE:
Access Type
Item
Number of bits
Read
Write
Accessing MII Registers
32 consecutive 1s
Write of 01 indicating start of frame
Write of code indicating access type
This bit changes depending on the PHY-LSI address.
This bit changes depending on the PHY-LSI register address.
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) performed
16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performed
(b) Read: Bus already released in TA; control unnecessary
PRE
1..1
1..1
32
Figure 9.5 MII Management Frame Format
ST
01
01
2
OP
10
01
2
MII Management Frame
PHYAD
00001
00001
5
RRRRR
RRRRR
REGAD
5
TA
Z0
10
2
DATA
D..D
D..D
16
IDLE
X
403