HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 392

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

9.2
9.2.1
The EtherC mode register specifies the operating mode of the Ethernet controller. The settings in
this register are normally made in the initialization process following a reset.
Note: Operating mode settings must not be changed while the transmitter and receiver are
Bits 31 to 13—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 12—Permit Receive CRC Error Frame (PRCEF): Specifies the treatment of a receive frame
containing a CRC error.
Bit 12: PRCEF
0
1
Note: When this bit is set to 1, the CRC error frame counter register (CEFCR: see section 9.2.14)
376
Initial value:
Initial value:
Initial value:
is not incremented when a CRC error is detected.
enabled. To modify the operating mode settings or change the operating mode while the
EtherC is running, first return the EtherC and E-DMAC modules to their initial state by
means of the software reset bit (SWR) in the E-DMAC mode register (EDMR), then make
new settings.
Register Descriptions
EtherC Mode Register (ECMR)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Description
Reception of a frame with a CRC error is treated as an error
Reception of a frame with a CRC error is not treated as an error
31
—
15
—
—
0
R
0
R
7
0
R
R/W
RE
30
—
14
—
0
R
0
R
6
0
R/W
TE
29
—
13
—
0
R
0
R
5
0
PRCEF
R/W
. . .
. . .
. . .
. . .
12
—
0
4
0
R
R/W
ILB
19
—
11
—
0
R
0
R
3
0
ELB
R/W
18
—
10
—
0
R
0
R
2
0
MPDE
R/W
R/W
DM
17
—
0
R
9
0
1
0
(Initial value)
PRM
R/W
16
—
—
0
R
8
0
R
0
0