HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 451

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

10.2.13 E-DMAC Operation Control Register (EDOCR)
EDOCR specifies the control methods used in E-DMAC operation.
Bits 31 to 3—Reserved: These bits should only be written with 0.
Bit 2—FIFO Error Control (FEC): Specifies E-DMAC operation when transmit FIFO underflow
or receive FIFO overflow occurs.
Bit 2: FEC
0
1
Bit 1—Address Error Control (AEC): Indicates detection of an illegal memory address in an
attempted E-DMAC transfer.
Bit 1: AEC
0
1
Note: This error occurs if the memory address setting in the descriptor used by the E-DMAC is
Bit 0—E-DMAC Halted (EDH): When the SH7615’s NMI input pin is asserted, E-DMAC
operation is halted.
Bit 0: EDH
0
1
436
Initial value:
Initial value:
illegal.
R/W:
R/W:
Bit:
Bit:
Description
E-DMAC operation continues when underflow or overflow occurs (Initial value)
E-DMAC operation halts when underflow or overflow occurs
Description
Illegal memory address not detected (normal operation)
Illegal memory address detected. Can be cleared by writing 0
Description
The E-DMAC is operating normally
The E-DMAC has been halted by NMI pin assertion. E-DMAC operation is
restarted by writing 0
31
—
—
—
—
0
7
0
30
—
—
—
—
0
6
0
29
—
—
—
—
0
5
0
. . .
. . .
. . .
. . .
—
—
4
0
11
—
—
—
—
0
3
0
FEC
R/W
10
—
—
0
2
0
AEC
R/W
—
—
9
0
1
0
(Initial value)
(Initial value)
EDH
R/W
—
—
8
0
0
0