HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 407

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

9.2.14
CEFCR is a 16-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'FFFF (65,535), the count is halted. The counter
value is cleared to 0 by a write to this register (the write value is immaterial).
Bits 31 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 15 to 0—CRC Error Frame Count 15 to 0 (CEFC15 to CEFC0): These bits indicate the count
of CRC error frames received.
Note: When the Permit Receive CRC Error Frame bit (PRCEF) is set to 1 in the EtherC Mode
Initial value:
Initial value:
Initial value:
Register (ECMR), CEFCR is not incremented by reception of a frame with a CRC error.
CRC Error Frame Counter Register (CEFCR)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
CEFC15 CEFC14 CEFC13 CEFC12 CEFC11 CEFC10 CEFC9
CEFC7
R/W
R/W
31
—
15
0
R
0
7
0
CEFC6
R/W
R/W
30
—
14
0
R
0
6
0
CEFC5
R/W
R/W
29
—
13
0
R
0
5
0
CEFC4
R/W
R/W
. . .
. . .
. . .
. . .
12
0
4
0
CEFC3
R/W
R/W
19
—
11
0
R
0
3
0
CEFC2
R/W
R/W
18
—
10
0
R
0
2
0
CEFC1
R/W
R/W
17
—
0
R
9
0
1
0
CEFC8
CEFC0
R/W
R/W
16
—
0
R
8
0
0
0
391