HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 503

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.3.5
The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus
state controller (BSC) just as it is when the CPU is the bus master. For details, see section 7, Bus
State Controller (BSC).
11.3.6
DMA transfer request acknowledge signal DACKn is output synchronous to the DMA address
output specified by the channel control register AM bit of the address bus. Normally, the
acknowledge signal becomes valid when DMA address output begins, and becomes invalid 0.5
cycles before the address output ends. (See figure 11.13.) The output timing of the acknowledge
signal varies with the settings of the connected memory space. The output timing of acknowledge
signals in the memory spaces is shown in figure 11.13.
Acknowledge Signal Output when External Memory Is Set as Ordinary Memory Space:
The timing at which the acknowledge signal is output is the same in the DMA read and write
cycles specified by the AM bit (figures 11.14 and 11.15). When DMA address output begins, the
acknowledge signal becomes valid; 0.5 cycles before address output ends, it becomes invalid. If a
wait is inserted in this period and address output is extended, the acknowledge signal is also
extended.
488
Number of Bus Cycles
DMA Transfer Request Acknowledge Signal Output Timing
(Active high)
Address bus
Figure 11.13 Example of DACKn Output Timing
DACKn
Clock
CPU
DMAC
0.5 cycles