HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 9

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Section 7
7.1
7.2
7.3
7.4
7.5
7.6
Overview............................................................................................................................ 249
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions ......................................................................................................... 257
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 274
Access Size and Data Alignment ....................................................................................... 275
7.3.1
7.3.2
Accessing Ordinary Space ................................................................................................. 278
7.4.1
7.4.2
7.4.3
Synchronous DRAM Interface .......................................................................................... 288
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 Power-On Sequence.............................................................................................. 317
7.5.11 64 Mbit Synchronous DRAM (2 Mword 32 Bit) Connection........................... 319
DRAM Interface ................................................................................................................ 320
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
Bus State Controller (BSC)
Features ................................................................................................................. 249
Block Diagram...................................................................................................... 251
Pin Configuration.................................................................................................. 252
Register Configuration.......................................................................................... 254
Address Map ......................................................................................................... 255
Bus Control Register 1 (BCR1)............................................................................ 257
Bus Control Register 2 (BCR2)............................................................................ 260
Bus Control Register 3 (BCR3)............................................................................ 261
Wait Control Register 1 (WCR1) ......................................................................... 263
Wait Control Register 2 (WCR2) ......................................................................... 265
Wait Control Register 3 (WCR3) ......................................................................... 267
Individual Memory Control Register (MCR) ....................................................... 268
Refresh Timer Control/Status Register (RTCSR) ................................................ 272
Refresh Timer Counter (RTCNT) ........................................................................ 274
Connection to Ordinary Devices .......................................................................... 275
Connection to Little-Endian Devices.................................................................... 277
Basic Timing......................................................................................................... 278
Wait State Control ................................................................................................ 283
CS Assertion Period Extension ............................................................................ 287
Synchronous DRAM Direct Connection .............................................................. 288
Address Multiplexing............................................................................................ 290
Burst Reads ........................................................................................................... 292
Single Reads.......................................................................................................... 297
Single Writes ........................................................................................................ 299
Burst Write Mode ................................................................................................. 300
Bank Active Function ........................................................................................... 303
Refreshes............................................................................................................... 313
Overlap Between Auto Precharge Cycle (Tap) and Next Access ........................ 316
DRAM Direct Connection.................................................................................... 320
Address Multiplexing............................................................................................ 321
Basic Timing......................................................................................................... 322
Wait State Control ................................................................................................ 323
Burst Access.......................................................................................................... 325
.......................................................................... 249
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