HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 627

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Note: With an 8-bit, 1-stop-bit format, one etu is equivalent to 1.5 frames.
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Receive FIFO Control in Error Data Reception
When data is transferred from SCRSR to the receive FIFO, the P and F flags are also
transferred. If either of these flags is set to 1, the error counter is incremented and the
corresponding bit (PER3 to PER0, FER3 to FER0) is updated in the serial status 1 register
(SC1SSR). The error counter is decremented if the P or F flag is 1 when data in the receive
FIFO is read by the CPU or DMAC. The settings of the P and F flags for the read receive data
are also reflected in the PER and FER flags in SC1SSR. PER and FER are set when data
containing a parity error or framing error is read from the receive FIFO; they are not set when
serial data containing a parity error or framing error is received from the RxD pin. PER and
FER are cleared when data with no parity error or framing error is read from the receive FIFO.
This data is transferred to the receive FIFO even if it contains a parity error or framing error.
Whether or not the receive operation is to be continued at this point can be specified with the
EI bit in SC2SSR. If the EI bit is set to 1, specifying continuation of the receive operation,
receive data is still transferred sequentially to the receive FIFO after an error occurs. The stage
of the 16-stage FIFO buffer in which the data with the error is located can be determined by
reading bits ED15 to ED0 in the FIFO error register (SCFER).
When the receive trigger number is set and receive data is read from the receive FIFO by the
DMAC, care must be taken not to read data exceeding the receive trigger number indicated by
the FIFO control register (SCFCR) (see section 14.2.10).
Receive FIFO Control by DR Flag
When a number of data bytes equal to or exceeding the receive trigger number have been
received, a receive data read request is issued to the CPU or DMAC by means of an RXI
interrupt (RDF only). However, an RXI interrupt is not requested if all reception has been
completed with fewer than the receive trigger number of data bytes having been received. In
this case, the DR flag is set and an ERI interrupt is requested 15 etu after reception of the last
data is completed. The CPU should therefore read bits R4 to R0 in SCFDR to find the number
of data bytes left in the receive FIFO, and read all the data in the FIFO.
etu: Elementary time unit = sec/bit