HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 155

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

4.6
When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in
table 4.10. When this happens, it will be accepted when an instruction for which exception
acceptance is possible is decoded.
Table 4.10 Exception Source Generation Immediately after a Delayed Branch Instruction
Point of Occurrence
Immediately after a delayed branch instruction*
Immediately after an interrupt-disabled instruction*
A repeat loop comprising up to three instructions (instruction
fetch cycle not generated)
First instruction or last three instructions in a repeat loop
containing four or more instructions
Fourth from last instruction in a repeat loop containing four
or more instructions
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
4.6.1
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction located immediately after it (delay slot) are always executed consecutively, so no
exception handling occurs between the two.
4.6.2
When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts
are not accepted. Address errors are accepted.
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
When Exception Sources Are Not Accepted
Immediately after a Delayed Branch Instruction
Immediately after an Interrupt-Disabled Instruction
BRAF
or Interrupt-Disabled Instruction
1
2
Address Error
Not accepted
Accepted
Not accepted
Accepted
Exception Source
Interrupt
Not accepted
Not accepted
Not accepted
Not accepted
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