HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 695

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

16.4.5
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
The correspondence between PWM output pins and registers is shown in table 16.6.
PWM mode 1
PWM output is generated by pairing TGRA with TGRB and TGRC with TGRD. The output
specified by bits IOA3–IOA0 and IOC3–IOC0 in TIOR is performed in response to compare
match A and C, and the output specified by bits IOB3–IOB0 and IOD3–IOD0 in TIOR in
response to compare match B and D, from pins TIOCA and TIOCC. The initial output value is
the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output
value does not change when a compare match occurs.
In PWM mode 1, a maximum 4-phase PWM output is possible.
PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified by TIOR is performed in response to a compare match. Also, when the
counter is cleared by a synchronization register compare match, pin output values are the initial
values set in TIOR. If the set values of the period and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with
synchronous operation.
PWM Modes
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