HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 595

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 14.9 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR
Bit 7:
C/A
0
1
14.3.2
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure,
so that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 14.3 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCIF monitors the line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (LSB-first
or MSB-first order selectable), a parity bit or multiprocessor bit (high or low level), and finally
one or two stop bits (high level).
582
Operation in Asynchronous Mode
Bit 1:
CKE1
0
1
0
1
SCSCR Setting
Bit 0:
CKE0
0
1
0
1
0
1
0
1
Mode
Asynchronous
mode
Synchronous
mode
Clock
Source
Internal
External
Internal
External
SCIF Transmit/Receive Clock
SCK Pin Function
SCIF does not use SCK pin
16/8/4 times bit rate
Inputs clock with frequency of 16/8/4
times bit rate
Outputs serial clock
Inputs serial clock
Outputs clock with frequency of