HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 459

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Tx Descriptor 2 (TD2): Specifies the 32-bit transmit buffer start address.
Note: The address specification must align with a 16-byte boundary.
Bits 31 to 0—Tx Buffer Address (TBA)
Receive Descriptor
Figure 10.3 shows the relationship between a receive descriptor and the receive buffer. In frame
reception, the E-DMAC performs data rewriting up to a receive buffer 16-byte boundary,
regardless of the receive frame length. Finally, the actual receive frame length is reported in the
lower 16 bits of RD1 in the descriptor. Data transfer to the receive buffer is performed
automatically by the E-DMAC to give a one frame/one buffer or one frame/multi-buffer
configuration according to the size of one received frame.
Note: The descriptor and receive buffer start address settings must align with a 16-byte
444
RD0
RD1
RD2
boundary.
Make the setting so that the size of the receive buffer aligns with a 16-byte boundary.
Example: H'0500 (= 1536 bytes)
Figure 10.3 Relationship between Receive Descriptor and Receive Buffer
Receive descriptor
31 30 29 28
31
31
RBL
27
26
Padding (4 bytes)
RFS 26 to RFS0
15 16
RBA
RDL
0
0
Receive buffer
Valid receive data