HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 490

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.3.3
When the DMAC receives simultaneous transfer requests on two channels, it selects a channel
according to a predetermined priority order. There is a choice of two priority modes, fixed or
round-robin. The mode is selected by the priority bit, PR, in the DMA operation register
(DMAOR).
Fixed Priority Mode: In this mode, the relative channel priority levels are fixed. When PR is set
to 0, channel 0 has higher priority than channel 1. Figure 11.3 shows an example of a transfer in
burst mode.
In cycle-steal mode, once a channel 0 request is accepted, channel 1 requests are also accepted
until the next request is accepted, which makes more effective use of the bus cycle. If requests
come simultaneously for channel 0 and channel 1 when DMA operation is starting, the first is
transmitted with channel 0, and thereafter channel 1 and channel 0 transfers are performed
alternately.
DREQ0
DREQ1
DREQ0
DREQ1
cycle
cycle
Bus
Bus
Channel Priorities
CPU
CPU
Figure 11.4 Fixed Mode DMA Transfer in Cycle-Steal Mode
Figure 11.3 Fixed Mode DMA Transfer in Burst Mode
CPU
(Dual Address, DREQ Falling-Edge Detection)
CPU
(Dual Address, DREQ Low-Level Detection)
CPU
CPU
Channel 0
source
Channel 0
source
destination
Channel 0
destination
Channel 0
CPU
Channel 0
source
Channel 1
source
destination
Channel 0
destination
Channel 1
Channel 1
source
CPU
destination
Channel 1
Channel 0
source
475