HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 94

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

The instruction codes, operation, and execution states of the CPU instructions are listed by
classification with the formats listed in below.
Instruction
Indicated by mnemonic
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums.
76
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
2. Depending on the instruction’s operand size, scaling is 1, 2, or 4. For details, see
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory
same.
the SH-1/SH-2/SH-DSP Programming Manual.
2
Instruction Code
Indicated in MSB
LSB order
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
0000: R0
0001: R1
.........
1111: R15
register) and the register used by the next instruction are the
Operation
Indicates summary of
operation
Explanation of Symbols
(xx): Memory operand
M/Q/T: Flag bits in the SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive OR of each bit
~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
,
: Transfer direction
Execution
Cycles
Value when
no wait
states are
inserted*
1
T Bit
Value of T bit
after
instruction is
executed
Explanation of
Symbols
—: No change