HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 663

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

16.2.2
Channel 0: TMDR0
Channel 1: TMDR1
Channel 2: TMDR2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has three TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset.
TCNT operation should be stopped when making TMDR settings.
Bits 7 and 6—Reserved: These bits are always read as 1. The write value should always be 0.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be
modified.
Bit 5: BFB
0
1
Initial value:
Initial value:
Timer Mode Register (TMDR)
R/W:
R/W:
Bit:
Bit:
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
—
—
7
1
R
7
1
R
—
—
6
1
R
6
1
R
BFB
R/W
—
5
0
5
0
R
BFA
R/W
—
4
0
4
0
R
MD3
MD3
R/W
R/W
3
0
3
0
MD2
MD2
R/W
R/W
2
0
2
0
MD1
MD1
R/W
R/W
1
0
1
0
(Initial value)
MD0
MD0
R/W
R/W
0
0
0
0
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