HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 142

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 4.1
Exception
Reset
Address
error
Interrupt
Instructions Trap instruction (TRAPA)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
124
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BRAF
BF/S, BT/S, BSRF, BRAF
Types of Exception Handling and Priority Order
Source
Power-on reset
Manual reset
CPU address error
DMA address error (DMAC and E-DMAC)
NMI
User break
Hitachi user debug interface (H-UDI)
External interrupts (IRL1–IRL15, IRQ0–IRQ3 (set with IRL3, IRL2, IRL1,
IRL0 pins))
On-chip peripheral modules
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly following a delayed
branch instruction
*1
or instructions that rewrite the PC
Direct memory access controller (DMAC)
Watchdog timer (WDT)
Compare match interrupt (part of the bus
state controller)
Ethernet controller (EtherC) and Ethernet
controller direct memory access controller
(E-DMAC)
16-bit free-running timer (FRT)
Serial communication interface with FIFO
(SCIF)
16-bit timer pulse unit (TPU)
Serial I/O (SIO)
*2
)
Priority
High
Low