HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 482

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.2.7
Note: * Only 0 can be written, to clear the flag.
The DMA operation register (DMAOR) is a 32-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. Only the lower four of the 32 bits are
valid. DMAOR is written as a 32-bit value, including the upper 28 bits. Write the initial values to
the upper 28 bits. These bits always read 0. DMAOR is initialized to H'00000000 by a reset and in
standby mode. It retains its value when the module standby function is used.
Bits 31 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Priority Mode Bit (PR): Specifies whether a fixed channel priority order or round-robin
mode is to be used there are simultaneous transfer requests for multiple channels. It is initialized to
0 by a reset and in standby mode. It retains its value when the module standby function is used.
Bit 3: PR
0
1
Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in the
DMAC. When the AE bit is set to 1, DMA transfer cannot be enabled even if the DE bit in the
DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it and then
write 0. Operation is performed up to the DMAC transfer being executed when the address error
occurred. AE is initialized to 0 by a reset and in standby mode. It retains its value when the
module standby function is used.
Initial value:
Initial value:
DMA Operation Register (DMAOR)
R/W:
R/W:
Bit:
Bit:
31
—
—
0
R
7
0
R
Description
Fixed priority (channel 0 > channel 1)
Round-robin (Top priority shifts to bottom after each transfer. The
priority for the first DMA transfer after a reset is channel 1 > channel 0)
30
—
—
0
R
6
0
R
29
—
—
0
R
5
0
R
…
…
…
…
—
4
0
R
R/W
PR
11
—
0
R
3
0
R/(W)*
AE
10
—
0
R
2
0
R/(W)*
NMIF
—
9
0
R
1
0
(Initial value)
DME
R/W
—
8
0
R
0
0
467