HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 646

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

15.2.6
Note: * Only 0 should be written, to clear the flag.
SISTR is a 16-bit register that indicates the status of the serial I/O module. SISTR is initialized to
H'0002 by a reset.
Bits 15 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit
underrun.
Bit 3: TERR
0
1
Bit 2—Receive Overrun Error (RERR): Flag that indicates the occurrence of a receive overrun.
Bit 2: RERR
0
1
Initial value:
Serial Status Register (SISTR)
R/W:
Bit:
Description
Transmission is in progress, or has ended normally
TERR is cleared to 0 in the following cases:
A transmit underrun error has occurred
TERR is set to 1 if data transmission is started while TDRE = 1
Description
Reception is in progress, or has ended normally
RERR is cleared to 0 in the following cases:
A receive overrun error has occurred
RERR is set to 1 if data reception ends while RDRE = 1
15
—
0
R
When 0 is written to the TERR bit after reading TERR = 1
When the processor enters the reset state
When 0 is written to the RERR bit after reading RERR = 1
When the processor enters the reset state
14
—
0
R
...
...
...
...
—
4
0
R
R/(W)*
TERR
3
0
R/(W)*
RERR
2
0
R/(W)*
TDRE
1
1
(Initial value)
(Initial value)
R/(W)*
RDRF
0
0
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