HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 221

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 31 to 0:
BAMAn
0
1
Note: n = 31 to 0
6.2.3
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that sets four channel A
break conditions: (1) CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle, (2) instruction
fetch/data access, (3) read/write, and (4) operand size. BBRA is initialized to H'0000 by a power-
on reset; after a manual reset, its value is undefined.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU/DMAC, E-DMAC Cycle Select A (CPA1, CPA0): These bits specify whether
a CPU cycle, or a DMAC or E-DMAC cycle, is to be selected as the bus cycle used as a channel A
break condition.
Bit 7:
CPA1
0
1
Initial value:
Initial value:
Break Bus Cycle Register A (BBRA)
Bit 6:
CPA0
0
1
0
1
R/W:
R/W:
Bit:
Bit:
Description
Channel A break address bit BAAn is included in break condition (Initial value)
Channel A break address bit BAAn is masked, and not included in condition
CPA1
R/W
15
—
Description
Channel A user break interrupt is not generated
CPU cycle is selected as user break condition
DMAC or E-DMAC cycle is selected as user break condition
CPU, DMAC, or E-DMAC cycle is selected as user break condition
0
R
7
0
CPA0
R/W
14
—
0
R
6
0
IDA1
R/W
13
—
0
R
5
0
IDA0
R/W
12
—
0
R
4
0
RWA1
R/W
11
—
0
R
3
0
RWA0
R/W
10
—
0
R
2
0
SZA1
R/W
—
9
0
R
1
0
(Initial value)
SZA0
R/W
—
8
0
R
0
0
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