HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 178

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

5.3.4
Interrupt priority level setting register D (IPRD) is a 16-bit read/write register that sets the priority
levels (0–15) of on-chip peripheral module interrupts. IPRD is initialized to H'0000 by a reset. It is
not initialized in standby mode.
Bits 15 to 4—16-Bit Timer Pulse Unit 0 to 2 (TPU0–TPU2) Interrupt Priority Level 3 to 0
(TPUnIP3–TPUnIP0, n = 0–2): These bits set the 16-bit timer pulse unit 0 to 2 (TPU0–TPU2)
interrupt priority levels. There are four bits for each interrupt, so the value can be set between 0
and 15.
Bits 3 to 0—Serial Communication Interface with FIFO 1 (SCIF1) Interrupt Priority Level 3 to 0
(SCF1IP3–SCF1IP0): These bits set the serial communication interface with FIFO 1 (SCIF1)
interrupt priority level. There are four bits, so the value can be set between 0 and 15.
160
Initial value:
Initial value:
Interrupt Priority Level Setting Register D (IPRD)
R/W:
R/W:
Bit:
Bit:
TPU0IP3 TPU0IP2 TPU0IP1 TPU0IP0 TPU1IP3 TPU1IP2 TPU1IP1 TPU1IP0
TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
R/W
R/W
8
0
0
0