HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 321

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

cycle, the DQMxx signal for the Td1 cycle data output cannot be specified. This is why the Tnop
cycle is inserted. When the CAS latency is 2 or more, however, the Tnop cycle is not inserted so
that timing requirements will be met even when a DQMxx signal is set after the Tc cycle.
When the bank active mode is set, the access will start with figure 7.24 or figure 7.27 and repeat
figure 7.25 or figure 7.28 for as long as the same row address continues to be accessed when only
accesses to the respective banks of the CS3 space are considered. Accesses to other CS spaces
during this period do not affect this operation. When an access occurs to a different row address
while the bank is active, figure 7.26 or figure 7.29 will be substituted for figures 7.25 and 7.28
after this is detected. Both banks will become inactive even in the bank active mode after the
refresh cycle ends or after the bus is released by bus arbitration.
304
CKIO
A24–A11
A10
A9–A1
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31–D0
DACKn*
Note: * DACKn waveform when active-low is specified.
Figure 7.24 (a) Burst Read Timing (No Precharge) I : E = 1 : 1
Tr
Tc
Td1
Td2
Td3
Td4
Tde