HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 431

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 0: SWR
0
1
Notes: If the EtherC and E-DMAC are initialized by means of this register during data transmission,
10.2.2
The E-DMAC transmit request register issues transmit directives to the E-DMAC.
Bits 31 to 1—Reserved: These bits should only be written with 0.
Bit 0—Transmit Request (TR): When 1 is written to this bit, the E-DMAC reads a descriptor, and
in the case of an active descriptor, transfers the data in the transmit buffer to the EtherC.
Bit 0: TR
0
1
Note: When transmission of one frame is completed, the next descriptor is read. If the transmit
416
Initial value:
Initial value:
etc., abnormal data may be sent onto the line.
The EtherC and E-DMAC are initialized in 16 internal clocks. Therefore, before accessing
registers in the EtherC and E-DMAC, 16 internal clocks must be waited for.
active bit in this descriptor has the “active” setting, transmission is continued. If the transmit
active bit has the “inactive” setting, the TR bit is cleared and operation of the transmit
DMAC is halted.
E-DMAC Transmit Request Register (EDTRR)
R/W:
R/W:
Bit:
Bit:
Description
EtherC and E-DMAC reset is cleared
EtherC and E-DMAC are reset
Description
Transmission-halted state. Writing 0 does not stop transmission. Termination of
transmission is controlled by the active bit in the transmit descriptor
Start of transmission. The relevant descriptor is read and a frame is sent with
the transmit active bit set to 1
31
—
—
—
—
0
7
0
30
—
—
—
—
0
6
0
29
—
—
—
—
0
5
0
. . .
. . .
. . .
. . .
—
—
4
0
11
—
—
—
—
0
3
0
10
—
—
—
—
0
2
0
—
—
—
—
9
0
1
0
(Initial value)
R/W
TR
—
—
8
0
0
0