HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 512

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Acknowledge Signal Output when External Memory Is Set as DRAM: When external memory
is set as DRAM and a row address is output during a read or write, the acknowledge signal is
output across the row address and column address (figures 11.29–11.31).
Clock
Bus cycle
DREQn
(Active high)
DACKn
(Active high)
RAS
CAS
RD/WR
WEn/DQMxx
(Active high)
Figure 11.29 DACKn Output in Normal DRAM Accesses (AM = 0 or 1)
Address
Figure 11.28 (b) Synchronous DRAM One-Cycle Write Timing
DACKn
Clock
Acceptance
bus
CPU
Blind zone
CPU
DACK1
Precharge
DMAC1
DMAC read or write
DACK2
DMAC2 DMAC3 DMAC4
address
(basic timing)
Row
DACK3
Column address
DACK4
CPU
CPU
. . . .
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