HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 523

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.5
1. DMA request/response selection control registers 0 and 1 (DRCR0 and DRCR1) should be
2. Before rewriting a register in the DMAC, first clear the DE bit to 0 in the CHCR register for
3. When the DMAC is not operating, the NMIF bit in DMAOR is set even when an NMI
4. The DMAC cannot access the cache memory.
5. Before changing the frequency or changing to standby mode, set the DME bit of DMAOR to 0
6. Do not use the DMAC, BSC, UBC, E-DMAC, and EtherC for on-chip peripheral module
7. Do not access the cache (address array, data array, associative purge area).
8. Note that when level detection of the request signal is used in single address mode, the request
9. When E exceeds 30 MHz, do not use transfer involving DACK output on ordinary space for
10. When DMA transfer is performed in response to a DMA transfer request signal from a
508
accessed in bytes. All other registers should be accessed in longword units.
the specified channel, or clear the DME bit in DMAOR to 0.
interrupt is input.
and stop operation of the DMAC.
transfers.
signal may be detected before DACK is output.
word or longword access with an 8-bit bus width, or longword access with a 16-bit bus width.
peripheral module, if clearing of the DMA transfer request signal from the peripheral module
by the DMA transfer is not completed before the next transfer request signal from that module,
subsequent DMA transfers may not be possible.
Usage Notes