HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 134

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

FR3
0
0
0
0
1
1
1
1
1
1
Frequency Change: When PLL circuit 1 or PLL circuit 2 becomes operational after modifying
the frequency modification register (including modification the frequency modification register in
the operating state), access the frequency modification register using the following procedure, and
noting the cautions listed below.
Frequency change procedure
Sample code for changing the frequency is shown below.
116
Modes 0–6
PLL circuits 1 and 2 halted
EXTAL input or crystal resonator used (modes 0–3)
CKIO input (modes 4–6)
Note: Do not use combinations other than those shown above.
Set the on-chip watchdog timer (WDT) overflow time to secure the PLL circuit oscillation
settling time (CKS[2–0] bits in WTCSR).
Clear the WT/IT and TME bit to 0 in WTCSR.
Perform a read anywhere in an external memory area 0–4 cache-through area.
Change the frequency modification register to the target frequency, or change the
operating/halted state of the PLL circuits 1 and 2 (the clocks will stop temporarily inside the
chip).
The oscillation circuits operate, and the clock is supplied to the WDT. This clock increments
the WDT.
On WDT overflow, supply of a clock with the frequency set in frequency setting bits FR3–FR0
begins. In this case, the OVF bit in WTSCR and the WOVF bit in RSTCSR are not set, an
interval timer interrupt (ITI) is not requested, and the WDTOVF signal is not asserted.
FR2
0
1
1
1
0
0
0
1
1
1
FR1
0
0
0
1
0
0
1
0
1
1
FR0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
I
1/4
1/2
1/2
1/2
1
1
1
1
1
1
E
1/4
1/4
1/2
1/2
1/4
1/2
1/2
1
1
1
P
1/4
1/4
1/4
1/2
1/4
1/4
1/2
1/4
1/2
1
CKIO
1
1
1
1
1
1
1
1
1
1