HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 568

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

In IrDA communication mode, bit 5 is the IrDA clock select 2 (ICK2) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
Bit 4—Parity Mode (O/E)/IrDA Clock Select 1 (ICK1): Selects either even or odd parity for use in
parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling
parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in
synchronous mode, and when parity addition and checking is disabled in asynchronous mode.
Bit 4: O/E
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
In IrDA communication mode, bit 4 is the IrDA clock select 1 (ICK1) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
Bit 3—Stop Bit Length (STOP)/IrDA Clock Select 0 (ICK0): Selects 1 or 2 bits as the stop bit
length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When
synchronous mode is set, the STOP bit setting is invalid since stop bits are not added.
Bit 3: STOP
0
1
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
In IrDA communication mode, bit 3 is the IrDA clock select 0 (ICK0) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
before it is sent.
before it is sent.
Description
Even parity*
Odd parity*
Description
1 stop bit*
2 stop bits*
1
2
2
1
(Initial value)
(Initial value)
555