HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 497

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Note: * Access size permitted by peripheral module register used as transfer source or transfer
482
Transfer requests can be auto-request, external requests, or on-chip peripheral module requests.
If the transfer request source is the SCIF or SIO, an SCIF or SIO register, respectively, must be
the transfer destination or transfer source (see table 11.6). For the combination of the
specifiable setting to perform data transfer using an external request (DREQ), see table 11.9.
Dual address mode outputs DACK in either the read cycle or write cycle. The
acknowledge/transfer mode bit (AM) of the DMA channel control registers 0 and 1 (CHCR0
and 1) specifies whether DACK is output in either the read cycle or the write cycle.
Figure 11.9 shows the DMA transfer timing in dual address mode.
D31–D0
A24–A0
(External Memory Space
DACK
CKIO
Transfer between on-chip peripheral module (excluding DMAC, BSC, UBC, cache, E-
DMAC, and EtherC) and on-chip peripheral module (excluding DMAC, BSC, UBC, cache,
E-DMAC, and EtherC)*
destination (excluding DMAC, BSC, UBC, cache, E-DMAC, and EtherC).
WE
BS
CS
RD
Figure 11.9 DMA Transfer Timing in Dual Address Mode
External Memory Space, DACK Output in Read Cycle)
Address output to
external memory space
Read strobe signal to
external memory space
Write strobe signal to
external memory space
I/O data of external
memory space
DMAC acknowledge signal
(active-low)