HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 416

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

1. When the receive enable (RE) bit is set, the receiver enters the receive idle state.
2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver
3. If the destination address matches the receiver’s own address, or if broadcast or multicast
4. Following data reception, the receiver carries out a CRC check. The result is indicated as a
5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode
400
SFD: Start frame delimitter
Note: The error frame also transmits data to the buffer.
starts receive processing.
transmission or promiscuous mode is specified, the receiver starts data reception.
status bit in the descriptor after the frame data has been written to memory.
register, the receiver prepares to receive the next frame.
Illegal carrier
Reception
detection
halted
Reset
RE set
RE reset
Figure 9.3 EtherC Receiver State Transitions
Idle
Error
notification
Preamble
detection
Promiscuous and other station
destination address
Normal reception
Start of frame
detection
reception
Error
Rx-DV negation
Receive error
detection
Receive
error
detection
Wait for SFD
Destination
reception
reception
reception
reception
address
CRC
Data
Own destination
address
or broadcast
or multicast
or promiscuous
End of
reception
SFD
reception