HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 279

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

according to the combination with the long wait specification bits (AnLW1 and AnLW0) in
BCR1, when the bits specifying the wait in the wait control register are set as long wait (i.e., are
set to 11). For a basic description of long waits, see section 7.2.1, Bus Control Register 1 (BCR1).
Bits 7 and 6—DMA Single-Write Wait (DSWW1, DSWW0): These bits determine the number of
wait states inserted between DACK assertion and CASn assertion when writing to DRAM or EDO
RAM in DMA single address mode.
Bit 7: DSWW1
0
1
Bits 5 to 3—Reserved bits: These bits are always read as 0. The write value should always be 0.
Bit 2—Number of Banks Specification when Using 64M Synchronous DRAM (BASEL): When
64M synchronous DRAM is specified by AMX2–AMX0 in MCR, the number of banks can be
specified.
Bit 2: BASEL
0
1
Bit 1—EDO Mode Specification (EDO): Enables EDO mode to be specified when DRAM is
specified for CS3 space.
Bit 1: EDO
0
1
Bit 0—Synchronous DRAM Burst Write Specification (BWE): Enables burst write mode to be
specified when synchronous DRAM is specified for CS2 or CS3 space.
Bit 0: BWE
0
1
262
Bit 6: DSWW0
0
1
0
1
Description
4 banks
2 banks
Description
High-speed page mode
EDO mode
Description
Single write mode
Burst write mode
Description
0 waits
1 wait
2 waits
Reserved (do not set)
(Initial value)
(Initial value)
(Initial value)
(Initial value)