HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 519

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

DREQ Pin Input Detection Timing in Burst Mode: In burst mode, the request detection timing
is different for edge detection and level detection of DREQn input.
With edge detection of DREQn input, once a request is detected, DMA transfer continues until the
transfer end condition is satisfied, regardless of the state of the DREQn pin. Request detection is
not performed during this time. When the transfer start conditions are fulfilled after the end of
transfer, request detection is performed again every cycle.
504
Clock
Bus cycle
Bus DREQn
(Active high)
DACKn
(Active high)
Figure 11.41 DREQn Pin Input Detection Timing in Burst Mode with Edge Detection
Figure 11.40 When an 8-Bit External Device is Connected (Level Detection)
(Active high)
(Active high)
Bus cycle
Acceptance
DREQn
DACKn
Clock
CPU
Blind zone
1st
acceptance
CPU
CPU
CPU
DMAC1
DACK
HH
DMAC
Blind zone
HH
DACK
HL
DMAC
DMAC2
HL
DACK
LH
DMAC
LH
DMAC3
2nd
acceptance
DACK
DMAC
LL
LL
Blind zone
DMAC4
CPU