HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 209

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 5.8
Item
Compare identified
interrupt priority with SR
mask level
Wait for completion of
sequence currently being
executed by CPU
Time from interrupt
exception handling (SR
and PC saves and vector
address fetch) until fetch of
first instruction of exception
service routine starts
Response time
Note: m1–m4 are the number of states needed for the following memory accesses
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch of first instruction of interrupt service routine
Icyc: I cycle time
Ecyc: E cycle time
Pcyc: P cycle time
Peripheral modules A: DMAC, REF (BSC)
Peripheral modules B: WDT, FRT, TPU, SCIF, SIO, E-DMAC
Interrupt Response Time
Maximum: 11 + 2 (m1
Minimum: 10
Total: X + 7.0
NMI
2.0
X ( 0)
5.0
+ m1 + m2
+ m3
+ m1 + m2
+ m3
+ m2 + m3)
+ m4
Icyc
Icyc
Icyc
IRL/IRQ
0.5
+ 1.0
+ 1.5
X ( 0)
5.0
+ m1 + m2
+ m3
X + 5.5
+ 1.0
+ 1.5
+ m1 + m2
+ m3
11
19.5 + 2 (m1
+ m2 + m3)
+ m4
Number of States
Icyc
Icyc
Ecyc
Pcyc
Ecyc
Pcyc
Icyc
A
0.5
+ 1.0
X ( 0)
5.0
+ m1 + m2
+ m3
X + 5.5
+ 1.0
+ m1 + m2
+ m3
9.5
13.5 + 2 (m1
+ m2 + m3)
+ m4
Peripheral Module
Icyc
Icyc
Pcyc
Pcyc
Icyc
B
1.0
X ( 0)
5.0
+ m1 + m2
+ m3
X + 5.0
+ 1.0
+ m1 + m2
+ m3
9
13.0 + 2 (m1
+ m2 + m3)
+ m4
Pcyc
Icyc
Pcyc
Icyc
Notes
The longest
sequence is for
interrupt or address-
error exception
handling (X = 4.0
Icyc + m1 + m2 +
m3 + m4). If an
interrupt-making
instruction follows,
however, the time
may be even longer
during repeat
instruction
execution
I :E :P = 1:1:1
I :E :P = 1:1/4:1/4
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