HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 661

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When a both-edges count is selected, a clock divided by two from the input clock can be selected.
(e.g. P /4 both edges = P /2 rising edge). If phase counting mode is used on channels 1, and 2,
this setting is ignored and the phase counting mode setting has priority.
Bit 4: CKEG1
0
1
Note: Internal clock edge selection is valid when the input clock is P /4 or slower. If P /1 is
Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT
counter clock. The clock source can be selected independently for each channel. Table 16.4 shows
the clock sources that can be set for each channel.
Table 16.4 TPU Clock Sources
Channel
0
1
2
Notes:
selected for the input clock, this setting is ignored and a rising-edge count is selected.
O
Blank: No setting
:
P /1
O
O
O
Setting
P /4
O
O
O
Bit 3: CKEG0
0
1
—
P /16 P /64 P /256 P /1024
O
O
O
Internal Clock
O
O
O
Description
Count at rising edge
Count at falling edge
Count at both edges
O
O
TCLKA TCLKB TCLKC TCLKD
O
O
O
O
O
O
External Clock
O
O
(Initial value)
O
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