HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 337

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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7.6
7.6.1
When the DRAM and other memory enable bits (DRAM2–DRAM0) in BCR1 are set to 010, the
CS3 space becomes DRAM space, and a DRAM interface function can be used to directly connect
DRAM.
The data width of an interface can be 16 or 32 bits (figures 7.33 and 7.34) Two-CAS 16-bit
DRAMs can be connected, since CAS is used to control byte access The RAS, CAS3, CAS2,
CAS1, CAS0, and RD/WR signals are used to connect the DRAM. When the data width is 16 bits,
CAS3, and CAS2 are not used. In addition to ordinary read and write access, burst access using
high-speed page mode is also supported
320
DRAM Interface
DRAM Direct Connection
Figure 7.35 Example of DRAM Connection (32-Bit Data Width)
Chip
RD/WR
CAS3
CAS2
CAS1
CAS0
RAS
D31
D16
D15
A10
D0
A2
256k
A8
A0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
A8
A0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
DRAM
16-bit

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