HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 365

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

The E-DMAC can perform access involving external memory, but not access involving any on-
chip memory or peripheral modules.
7.10.3
The SH7615 has two pins, STATS1 and STATS0, to identify the bus master status. The signals
output from these pins show the external access status. Encoded output is provided for the
following categories: CPU (cache hit/cache disable), DMAC (external access only), E-DMAC,
and Others (refresh, internal access, etc..). All output is synchronized with the address signals.
The encoding patterns are shown in table 7.9, and the output timing in figure 7.56.
Table 7.9
Identification
CPU
DMAC
E-DMAC
Others
7.10.4
The BUSHiZ pin is needed when the SH7615 is connected to a PCI controller via a PCI bridge,
and the PCI master and SH7615 share local memory on the SH7615 bus. By using this pin in
combination with the WAIT pin, it is possible to place the bus and specific control signals in the
high-impedance state while keeping the SH7615's internal state halted. The conditions for
establishing the high-impedance state, the applicable pins, and the bus timing (figure 7.57) are
shown below. See the Application Note for an example of PCI bridge connection.
348
CKIO
Address
CSn
STATS1, 0
Note: In on-chip I/O
accesses to on-chip I/O and on-chip RAM are included in the “Others” category.
STATS1 and STATS0 Pins
BUSHiZ Specification
Encoding Patterns
CPU
on-chip RAM or on-chip I/O
00
CPU
Figure 7.56 STATS Output Timing
STATS1
0
1
E-DMAC E-DMAC
memory transfers using the DMAC,
10
E-DMAC
E-DMAC G-DMAC G-DMAC G-DMAC
STATS0
0
1
0
1
01