HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 508

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

When external memory is set as bank active synchronous DRAM, during a burst read the
acknowledge signal is output across the read command, wait and read address when the row
address is the same as the previous address output (figure 11.22). When the row address is
different from the previous address, the acknowledge signal is output across the precharge, row
address, read command, wait and read address (figure 11.23).
(Active high)
(Active high)
Address
DACKn
Clock
Address
DACKn
bus
Clock
bus
Figure 11.22 DACKn Output in Synchronous DRAM Burst Read
Figure 11.23 DACKn Output in Synchronous DRAM Burst Read
CPU
(Bank Active, Different Row Address, AM = 0)
CPU
(Bank Active, Same Row Address, AM = 0)
charge
Pre-
command
address
Read
Row
(basic timing)
DMAC read
command
Read 1
Read
DMAC read (basic timing)
Read 1 Read 2 Read 3 Read 4
Read 2
Read 3
Read 4
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