HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 285

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 7 to 0—Area 3 to 0 CSn Assert Period Extension (A3SHW1–A0SHW0): These bits specify
the number of cycles from address/CSn output to RD/WEn assertion and from RD/WEn negation
to address/CSn hold for areas 3 to 0.
A3SHW1
A2SHW1
A1SHW1
A0SHW1
0
1
Note: * n = 0 to 3
7.2.7
The TRP1–TRP0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, BE, RASD, AMX2–AMX0
and SZ bits are initialized after a power-on reset. Do not write to them thereafter. When writing to
them, write the same values as they are initialized to. Do not access CS2 or CS3 until register
initialization is completed.
Bits 1 and 15—RAS Precharge Time (TRP1, TRP0): When DRAM is connected, specifies the
minimum number of cycles after RAS is negated before the next assert. When synchronous
DRAM is connected, specifies the minimum number of cycles after precharge until a bank active
command is output. See section 7.5, Synchronous DRAM Interface, for details.
268
Initial value:
Initial value:
Individual Memory Control Register (MCR)
R/W:
R/W:
Bit:
Bit:
A3SHW0
A2SHW0
A1SHW0
A0SHW0
0
1
0
1
AMX2
TRP0
R/W
R/W
15
0
7
0
RCD0
R/W
R/W
SZ
14
0
6
0
Description
0.5 cycle, CSn* hold cycle = 0 cycles
1.5 cycle, CSn* hold cycle = 1 cycle
2.5 cycle, CSn* hold cycle = 2 cycles
Reserved (do not set)
TRWL0
AMX1
R/W
R/W
13
0
5
0
TRAS1
AMX0
R/W
R/W
12
0
4
0
TRAS0
RFSH
R/W
R/W
11
0
3
0
RMODE
R/W
R/W
BE
10
0
2
0
RASD
TRP1
R/W
R/W
9
0
1
0
(Initial value)
TRWL1
RCD1
R/W
R/W
8
0
0
0