HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 484

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

11.3
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority; when the transfer-end conditions are satisfied, it ends the transfer.
Transfers can be requested in three modes: auto-request, external request, and on-chip module
request. A transfer can be in either single address mode or dual address mode. The bus mode can
be either burst or cycle-steal.
11.3.1
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (TCR), DMA channel control registers (CHCR), DMA vector number
registers (VCRDMA), DMA request/response selection control registers (DRCR), and DMA
operation register (DMAOR) are initialized (initializing sets each register so that ultimately the
condition (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0) is satisfied), the DMAC transfers data
according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0)
2. When a transfer request occurs and transfer is enabled, the DMAC transfers 1 transfer unit of
3. When the specified number of transfers have been completed (when TCR reaches 0), the
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
Figure 11.2 shows a flowchart illustrating this procedure.
data. (In auto-request mode, the transfer begins automatically after register initialization. The
TCR value will be decremented by 1.) The actual transfer flows vary depending on the address
mode and bus mode.
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt request is
sent to the CPU.
aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is
changed to 0.
Operation
DMA Transfer Flow
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