HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 469

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HD6417615

Manufacturer Part Number
HD6417615
Description
Hardware Manual
Manufacturer
Hitachi Semiconductor
Datasheet

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454
Transfer requests
Choice of bus mode
Choice of channel priority order
An interrupt request can be sent to the CPU on completion of data transfer
External request: from the DREQ pins. Edge or level detection, and active-low or active-
On-chip peripheral module requests: serial communication interface with FIFO (SCIF),
Auto-request: the transfer request is generated automatically within the DMAC
Cycle steal mode
Burst mode
Fixed mode
Round robin mode
high mode, can be specified for DREQ.
16-bit timer pulse unit (TPU), serial I/O (SIO)

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