HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 274

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.2
7.2.1
Initialize the ENDIAN, BSTROM, PSHR, and DRAM2–DRAM0 bits after a power-on reset, and
do not change their values thereafter. To change other bits by writing to them, write the same
value as they are initialized to. Do not access any space other than CS0 until the register
initialization ends.
Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 14 and 13—Long Wait Specification for Area 4 (A4LW1, A4LW0): From 3 to 14 wait cycles
are inserted in CS4 space accesses when the bits that specify the wait in the wait control register
specify long wait (i.e., are set to 11).
Bit 12—Endian Specification for Area 2 (A2ENDIAN): In big-endian format, the MSB of byte
data is the lowest byte address and byte data goes in order toward the LSB For little-endian
format, the LSB of byte data is the lowest byte address and byte data goes in order toward the
MSB When this bit is 1, the data is rearranged into little-endian format before transfer when the
CS2 space is read or written to. It is used when handling data with little-endian processors or
running programs written with conscious use of little-endian format.
Bit 12: A2ENDIAN
0
1
Initial value:
Initial value:
Register Descriptions
Bus Control Register 1 (BCR1)
R/W:
R/W:
Bit:
Bit:
A1LW1
R/W
15
—
0
R
7
1
Description
Big-endian
Little-endian
A4LW1
A1LW0
R/W
R/W
14
0
6
1
A0LW1
A4LW0
R/W
R/W
13
5
1
0
A0LW0
A2EN
DIAN
R/W
R/W
12
0
4
1
A4EN
DIAN
ROM
R/W
BST
R/W
11
3
0
0
DRAM2 DRAM1 DRAM0
R/W
10
—
0
R
2
0
AHLW1 AHLW0
R/W
R/W
9
1
1
0
(Initial value)
R/W
R/W
8
1
0
0
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