HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 349

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

7.6.7
Wait states equivalent to the value set in bits DSWW1 and DSWW0 in BCR3 can be inserted
between DACKn assertion and CASn assertion in a write in DMA single address transfer mode.
Inserting wait states allows the data setup time for external device memory. Figure 7.47 shows the
write cycle timing in DMA single transfer mode when DSWW1/DSWW0 = 01 and RASD = 1.
The DMA single transfer mode read cycle is the same as a CPU or DMA dual transfer mode read
cycle.
332
Read
Write
Note: * DACKn waveform when active-low is specified
DRAM Single Transfer
CKIO
A24–A16
A15–A1
RAS
CASn
D15–D0
CAS/OE
D15–D0
CAS/OE
DACKn *
RD/WR
Figure 7.46 DRAM EDO Mode Burst Access Timing
Tr
address
Row
Tc1
Column address
Tc2
Tc1
Column address
Row address
Tc2
High
Tc1
Column address
Tc2
Tc1
Column address
Tc2
(Tpc)