HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 202

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Table 5.6
Register
Vector number setting register R
Vector number setting register S
Vector number setting register T
Vector number setting register U
As table 5.6 shows, two on-chip peripheral module interrupts are assigned to each register. Set the
vector numbers by setting the corresponding 7-bit groups (bits 14 to 8 and bits 6 to 0) with values
in the range of H'00 (0000000) to H'7F (1111111). H'00 is vector number 0 (the lowest); H'7F is
vector number 127 (the highest). The vector table address is calculated by the following equation.
A reset initializes a vector number setting register to H'0000. They are not initialized in standby
mode.
Table 5.7
Register
Vector number setting register DMA0
(VCRDMA0)
Vector number setting register DMA1
(VCRDMA1)
As shown in table 5.7 the vector numbers for direct memory access controller transfer-end
interrupts are set in VCRDMA0 and VCRDMA1. See sections 11, Direct Memory Access
Controller, for more details.
184
Vector table address = VBR + (vector number
Interrupt Request Sources and Vector Number Setting Registers (1) (cont)
Interrupt Request Sources and Vector Number Setting Registers (2)
14–8
Receive overrun error interrupt
(SIO1)
Receive-data-full interrupt
(SIO1)
Receive overrun error interrupt
(SIO2)
Receive-data-full interrupt
(SIO2)
Bits
Setting Function
Channel 0 transfer end interrupt for DMAC
Channel 1 transfer end interrupt for DMAC
4)
6–0
Transmit underrun error
interrupt (SIO1)
Transmit-data-empty interrupt
(SIO1)
Transmit underrun error
interrupt (SIO2)
Transmit-data-empty interrupt
(SIO2)