HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 244

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 31—CPU Condition Match Flag A (CMFCA): This flag is set to 1 when a CPU bus cycle
condition, among the break conditions set for channel A, is satisfied. This flag is not cleared to 0
(if the flag setting is to be checked again after it has once been set, the flag must be cleared by a
write).
Bit 31: CMFCA
0
1
Bit 30—DMAC Condition Match Flag A (CMFPA): This flag is set to 1 when an on-chip DMAC
bus cycle condition, among the break conditions set for channel A, is satisfied. This flag is not
cleared to 0 (if the flag setting is to be checked again after it has once been set, the flag must be
cleared by a write).
Bit 30: CMFPA
0
1
Bits 29 and 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 27—PC Trace Enable (PCTE): Selects whether a PC trace is to be executed.
Bit 27: PCTE
0
1
Bit 26—PC Break Select A (PCBA): Selects whether a channel A instruction fetch cycle break is
effected before or after execution of the instruction.
Bit 26: PCBA
0
1
Bits 25 and 24—Reserved: These bits are always read as 0. The write value should always be 0.
226
Description
User break interrupt has not been generated by a channel A CPU cycle
condition
User break interrupt has been generated by a channel A CPU cycle condition
Description
User break interrupt has not been generated by a channel A on-chip DMAC
cycle condition
User break interrupt has been generated by a channel A on-chip DMAC cycle
condition
Description
PC trace is not executed
PC trace is executed
Description
Channel A instruction fetch cycle break is effected before instruction execution
Channel A instruction fetch cycle break is effected after instruction execution
(Initial value)
(Initial value)
(Initial value)
(Initial value)