HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 213

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

B. When clearing on-chip interrupt source
Synchronization instruction
RTE instruction
Delay slot instruction
Interrupt return destination instruction
On-chip peripheral interrupt
Interrupt clear instruction
When an interrupt source is from an on-chip peripheral module, also, pipeline operation
must be considered to ensure that the same interrupt is not implemented again. An interval
of 0.5 Icyc + 1.0 Pcyc is required until an on-chip peripheral module interrupt is identified
by the CPU. Similarly, an interval of 0.5 Icyc + 1.0 Pcyc is also necessary to report the fact
that an interrupt request is no longer present.
a. When returning from interrupt handling by means of RTE instruction
b. When changing level during interrupt handling
Figure 5.13 Pipeline Operation when Returning by Means of RTE Instruction
When the RTE instruction is used to return from interrupt handling, as shown in figure
5.13, consider the cycles to be inserted between the read instruction for synchronization
and the RTE instruction, according to the set clock ratio (I : E : P ).
The on-chip peripheral interrupt signal should be negated at least 0.5 Icyc + 1.0 Pcyc
before next interrupt acceptance becomes possible.
For example, if clock ratio I : E : P is 4 : 2 : 2, at least 2.5 Icyc should be inserted.
When the SR value is changed by means of an LDC instruction and multiple
implementation of other interrupts is enabled, consider the cycles to be inserted
between the synchronization instruction and the LDC instruction as shown in figure
5.14, according to the set clock ratio (I : E : P ).
The on-chip peripheral interrupt signal should be negated at least 0.5 Icyc + 1.0 Pcyc
before next interrupt acceptance becomes possible.
For example, if clock ratio I : E : P is 4 : 2 : 2, at least 2.5 Icyc should be inserted.
D
D
E
Write completed
M
E
D
M
E
On-chip peripheral
write, min. 1 Icyc
0.5Icyc + 1.0Pcyc
W
M
On-chip peripheral
read, min. 1 Icyc
M
Next interrupt can be accepted
D
F
E
D
E
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