HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 369

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

8.1
This chip incorporates 4 kbytes of four-way, mixed instruction/data type cache memory. This
memory can also be used as 2-kbyte RAM and 2 kbyte mixed instruction/data type cache memory
by making a setting in the cache control register (CCR) (two-way cache mode). CCR can specify
that either instructions or data do not use cache. Both write-through and write-back modes are
supported for cache operation.
Each line of cache memory consists of 16 bytes. Cache memory is always updated in line units.
Four 32-bit accesses are required to update a line. Since the number of entries is 64, the six bits
(A9 to A4) in each address determine the entry. A four-way set associative configuration is used,
so up to four different instructions/data can be stored in the cache even when entry addresses
match. To efficiently use four ways having the same entry address, replacement is provided based
on a pseudo-LRU (least-recently used) replacement algorithm.
The cache configuration is shown in figure 8.1, and addresses in figure 8.2.
V: Valid bit
U: Update bit
entries
64
Introduction
information
LRU
address bus
Cache address array
match signal
Tag address
Cache
address
Tag
Figure 8.1 Cache Configuration
Section 8 Cache
U
V
Internal
address bus
Cache data array
Data (16 bytes/line)
Cache
data bus
Internal
data bus
Way 0
Way 1
Way 2
Way 3
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