HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 222

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): These bits specify whether
an instruction fetch cycle or data access cycle is to be selected as the bus cycle used as a channel A
break condition.
Bit 5:
IDA1
0
1
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits specify whether a read cycle or
write cycle is to be selected as the bus cycle used as a channel A break condition.
Bit 3:
RWA1
0
1
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): These bits select the operand size of the bus
cycle used as a channel A break condition.
Bit 1:
SZA1
0
1
Notes: When a break is to be executed on an instruction fetch, clear the SZA0 bit to 0. All
204
instructions are regarded as being accessed using word size (instruction fetches are always
performed as longword).
In the case of an instruction, the operand size is word; in the case of a CPU/DMAC, E-
DMAC data access, it is determined by the specified operand size. Note that the operand
size is not determined by the bus width of the space accessed.
Bit 4:
IDA0
0
1
0
1
Bit 2:
RWA0
0
1
0
1
Bit 0:
SZA0
0
1
0
1
Description
Channel A user break interrupt is not generated
Instruction fetch cycle is selected as break condition
Data access cycle is selected as break condition
Instruction fetch cycle or data access cycle is selected as break condition
Description
Channel A user break interrupt is not generated
Read cycle is selected as break condition
Write cycle is selected as break condition
Read cycle or write cycle is selected as break condition
Description
Operand size is not included in break conditions
Byte access is selected as break condition
Word access is selected as break condition
Longword access is selected as break condition
(Initial value)
(Initial value)
(Initial value)