HD6417615 Hitachi Semiconductor, HD6417615 Datasheet - Page 372

• Manufacturer Part Number: HD6417615
• Description: Hardware Manual
• Manufacturer: Hitachi Semiconductor

Bit 1—Instruction Replacement Disable Bit (ID): ID is the bit for disabling instruction
replacement. When this bit is 1, an instruction fetched from external memory is not written to the
cache even if there is a cache miss. Cache data is, however, read or updated during cache hits. ID
is valid only when CE is 1.
Bit 1: ID
0
1
Bit 0—Cache Enable Bit (CE): CE is the cache enable bit. Cache can be used when CE is set to 1.
Bit 0: CE
0
1
8.3
The address space is divided into six partitions. The cache access operation is specified by
addresses. Table 8.2 lists the partitions and their cache operations. For more information on
address spaces, see section 7, Bus State Controller. Note that the spaces of the cache area and
cache-through area are the same.
Table 8.2
Addresses
A31–A29
000
001
010
011
110
111
356
Address Space and the Cache
Address Space and Cache Operation
Partition
Cache area
Cache-through area
Associative purge area
Address array read/write area
Data array read/write area
I/O area
Description
Normal operation
Data not replaced even when cache miss occurs in instruction fetch
Description
Cache disabled
Cache enabled
Cache Operation
Cache is used when the CE bit in CCR is 1
Cache is not used
Cache line of the specified address is purged
(disabled)
Cache address array is accessed directly
Cache data array is accessed directly
Cache is not used
(Initial value)
(Initial value)